This invention relates to a semiconductor device, and more particularly to a high-power and high-frequency device of self-biased type.
Microwave-semiconductor devices succh as Gallium Arsenide Schottky barrier field-effect transistors (GaAs FET), are well known from prior art (cf. Kazuhiko Honjo et al., "Broad-Band Internal Matching of Microwave Power GaAs MESFET's", IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-27, No. 1, January 1979, pp.-3 through 8, and Masumi Fukuta et al., "GaAs Microwave Power FET", IEEE Transactions on Electron Devices, Vol. ED-23, No. 4, April 1976, pp-388 through 394). Such a device includes one or more semiconductor chips. In order to improve the high-frequency characteristics of such a device, it is essential to have a small grounding inductance. For decreasing inductance, these semiconductor chips are assembled on a base made of, for example, copper with a film of gold plating, so as to shorten the length of the wire connected between the source electrode of one chip and the ground.
FIG. 1 is a circuit diagram illustrating a generally known FET assembled on a metal base. As shown illustrated in FIG. 1, the source electrode of this FET chip is connected to the ground through a wire having an inductance L.sub.0. Various steps have been successfully taken to reduce the inductance of the wire connected between the source electrode and the ground (see the above-mentioned references). In the circuit of this generally known type, the length of the wire can be made short because the distance between the source electrode and the ground is very short.
However, since the gate bias voltage must be lower than the source voltage, and the source voltage is zero volts because the source electrode is connected to ground through a conductive wire, such as a gold wire, a negative bias voltage.sup.-V GG is applied to the gate electrode of the FET chip of FIG. 1. Therefore, the circuit of FIG. 1 requires two power supplies, i.e., +V.sub.DD and -V.sub.GG.
In addition, when a drain voltage is applied to the drain without applying a gate bias voltage, the drain current will flow up to its maximum value, resulting in a higher channel temperature than the maximum safe channel temperature of the device. At such a high channel temperature the FET chip will be destroyed. To avoid destruction of the FET chip, it is necessary to apply a gate bias voltage before applying a drain voltage. This procedure of biasing is very troublesome.
In order to simplify the procedure of biasing and to reduce the number of power supplies, a known circuit of a self-biased FET, also assembled on a metal base, was proposed and is illustrated in FIG. 2. As illustrated in FIG. 2, a capacitor C and a resistor R.sub.S are connected in parallel between the source electrode of the FET chip and the metal base. A resistor R.sub.G is connected between the gate electrode of the FET chip and the ground. These resistors are connected outside the metal base. By this construction, high-frequency components of the current flowing through the source electrode are grounded through the capacitor C and DC components of the current pass through the resistor R.sub.S, resulting in the desired plus voltage at the source electrode of the FET chip. The direct current, conducted through the resistor R.sub.S, gives an appropriate bias voltage to the gate electrode of the FET chip. In the circuit of FIG. 2, only one power supply +V.sub.DD is required.
FIG. 3 illustrates a plan view of the circuit device of FIG. 2. A cross sectional view taken along the line IV--IV of FIG. 3 is illustrated in FIG. 4. Referring to FIGS. 3 and 4, the FET chip 3 and two capacitors 4a and 4b are mounted on a surface of a metal base 1 which forms the ground electrode. The metal base 1 is made of, for example, copper, and serves to ground high-frequency components through the two capacitors 4a and 4b, as well as to function as a heat sink. These capacitors 4a and 4b are both made of a dielectric, both sides of which are plated with metal. The sum of the capacities of the capacitors 4a and 4b is equal to the capacitance of the capacitor 4 in FIG. 2. The periphery of the surface of the metal base 1 is covered with a ceramic portion 2 which serves as an insulator. Two source leads 5a and 5b, an output lead 6, and an input lead 7 are arranged on the ceramic portion 2. These leads 5a, 5b, 6, and 7 are terminals for connecting this device assembled on this base to external devices or elements. The source electrode of the FET chip 3 is connected to the metal surfaces of the capacitors 4a and 4b through gold wires 8a and 8b respectively. The drain electrode of the FET chip 3 is connected to the output lead 6 through a gold wire 9. The gate electrode of the FET chip 3 is connected to the input lead 7 through a gold wire 10. The metal surfaces of the capacitors 4a and 4b are connected to the source leads 5a and 5b through gold wires 11a and 11b respectively. These gold wires 8a, 8b, 9, 10, 11a, and 11b may alternatively be gold ribbons. The resistors R.sub.S and R.sub.G in FIG. 2 are not shown in FIGS. 3 and 4 because they are connected outside the metal base.
The inductance which mainly affects the high-frequency characteeristics of the circuit device of FIG. 2 is that of the wire 8 (FIG. 2) between the source electrode of the FET chip 3 and the capacitor 4. This inductance is represented in FIGS. 3 and 4 by the gold wires 8a and 8b. As illustrated in FIGS. 3 and 4, since the capacitors 4a and 4b are arranged very close to the sides of the FET chip 3, the gold wires 8a and 8b can be very short, and thus, the grounding inductance is very small. Therefore, the self-biased GaAsFET device, as illustrated in FIGS. 2 through 4, has good high-frequency characteristics.
However, the above-mentioned FET device illustrated in FIGS. 2 through 4 can be used only for low power output devices. This is because, in order to limit the length of the wires 8a and 8b, the distance between the active area on the central portion of the FET chip 3 and a surface point of the capacitor 4a or 4b must be very short. If a high-power FET chip having an interdigitated-electrode structure (cf. above-mentioned reference "GaAs Microwave Power FET", by Fukuta et al.) is used in the arrangement of FIG. 3, the length of the wires 8a and 8b will be increased because the size of the high-power FET chip is greater than that of a low-power FET chip, so that the distance between the active area of the high-power FET chip and a surface point of the capacitor 4a or 4b will be increased. Therefore, the high-poweer FET device in the arrangement of FIG. 3 has a large grounding inductance, deteriorated high-frequency characteristics and low gain.
The inventors of the present application have investigated the possibility to improve device of FIG. 3 by providing a device as illustrated in FIG. 5, which is a plan-view of the high-power FET device. As illustrated in FIG. 5, a high-power FET chip 3 has a rectangular configuration due to its interdigitated-electrode structure. To avoid complexity, the interdigitated structure is not shown in FIG. 5. A capacitor 4 for conducting high-frequency components also has the same configuration as the FET chip 3. The FET chip 3 and the capacitor 4 are both mounted in parallel on the surface of a metal base 1 in such a way that the longitudinal direction of the FET chip 3 and the capacitor 4 is perpendicular to the extending direction of an input lead 7 and an output lead 6 which are arranged on a ceramic portion 2. Further, the capacitor 4 is arranged between the input lead 7 and the FET chip 3. The ceramic portion 2 covers the peripheral portion of the surface of the base 1 as in the case of FIG. 3. The source side of the chip 3 is connected to the metal surface of the capacitor 4 through four wires 81, 82, 83, and 84 having the same length. The drain side of the chip 3 is connected to the output lead 6 through four wires 91, 92, 93, and 94 having the same length. The gate side of the chip 3 is connected to the input lead 7 through four wires 101, 102, 103, and 104 having the same length. The surface of the capacitor 4 is connected to the source leads 5a and 5b, arranged in the same way as in the case of FIG. 3, through two wires 11a and 11b.
The equivalent circuit diagram of the FET device of FIG. 5 is the same as the circuit diagram illustrated in FIG. 2.
In the above-mentioned arrangement illustrated in FIG. 5, because the wires 81, 82, 83, and 84 connected between the source electrode of the chip 3 and the capacitor 4 all have the same short length, the grounding inductance between the source electrode of the chip 3 and the capacitor 4 is small.
However, the above-mentioned FET device illustrated in FIG. 5 does not make it possible to establish input-impedance matching satisfactorily. This is because the input impedance of a high-power transistor, such as the FET chip 3 in FIG. 5, is very small in comparison with the characteristic impedance of the input lead. The small input impedance is due to the large total gate width in a high power FET (such as an interdigitated FET) because, in the interdigitated structure, active FET regions connected in parallel offer a small input resistance. It is well known to represent input inpedance as an S-parameter S.sub.11. FIG. 6 is a Smith Chart illustrating the curve of an the S-parameter S.sub.11 of the GaAs power FET illustrated in FIG. 5. In the Smith Chart, the characteristic impedance of the input lead is 50.OMEGA. and is represented at the center of the chart. The S-parameter S.sub.11 varies along the curve S from the point P.sub.1 to the point P.sub.9 when the input frequency changes from 2 GHz to 10 GHz. As will be understood from the Smith Chart, the curve S is very close to the circle Ro of the chart, where the resistive component of the impedance would be equal to zero. This means that the resistance component of the input impedance of the high-power FET is very small, and that the higher the input frequency becomes (8, 9, 10 GHz), the higher the reactive component of the input impedance becomes, and thus, the higher the Q-value of the FET becomes. It is well known that the higher the Q-value, the more difficult it is to establish wide band matching i.e., the frequency range for impedance matching is very narrow. Moreover, in order to match the input impedance to the characteristic impedance of 50.OMEGA., it is necessary to increase the input impedance by connecting a capacitance to the input lead 7 (FIG. 5) at an appropriate point outside the base 1. FIG. 7 is an equivalent circuit diagram when the capacitor C is connected to the input lead 7 of the FET device of FIG. 5. As illustrated in FIG. 7, the FET chip 3 and the grounding capacitor 4 within the metal base 1 are inside the dotted line, and the capacitor C connected to the gate at the outside of the base 1 is outside the dotted line. Since the capacitor C for increasing the input impedance is connected outside of the base 1, the connecting lead between the gate and the capacitor C becomes long, resulting in a large inductance L.sub.1. The large inductance L.sub.1 causes an increase in the Q-value of the FET device. Therefore, it is very difficult to establish impedance matching, even when the capacitor C for impedance matching is inserted in the FET of FIG. 5.
Still another high-frequency semiconductor device was proposed in which a semiconductor chip and a capacitor for impedance matching are arranged in parallel between an input terminal and an output terminal of the semiconductor chip (cf. U.S. Pat. No. 4,042,952). The semiconductor chip and the capaccitor are mounted on a metal base which acts as a ground as well as a heat sink. However, in this device, because the semiconductor chip and the capacitor are insulated from the metal base, an input grounding terminal and an output grounding terminal are required, in addition to the input and output terminals. Further, a process of wire bonding to these grounding terminals is also required. Therefore the construction of the device is complex and the number of steps for manufacturing the device is increased. Moreover, this prior art does not disclose the semiconductor device of a self-biased type having a capacitor chip which includes both capacitors for input impedance matching and capacitors for grounding high-frequency components.